Platform-based IC (integrated circuit) design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs encountered in the current IC market. A platform is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) a customizable array of transistors; (3) an IP (intellectual property) block; (4) a processor, e.g., an ESP (embedded standard product); (5) an embedded programmable logic block; and (6) interconnect. RapidChip™ developed by LSI Logic Corp. is an instance of a platform. The basic idea behind the platform-based design is to avoid designing and manufacturing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Through extensive design reuse, the platform-based design may provide faster time-to-market and reduce design cost.
Under a platform approach, there are two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a slice is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers or top metal layers to be completed with the customer's unique IP. For example, RapidSlice™ developed by LSI Logic Corp. is an instance of a slice. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, portions of the metal layers are pre-specified to implement the pre-defined blocks of the platform and the diffusion processes are carried out in a wafer fab. The base characteristics, in terms of the IP, the processors, the memory, the interconnect, the programmable logic and the customizable transistor array, are all pre-placed in the design and pre-diffused in the slice. However, a slice is still fully decoupled because the customer has not yet introduced the function into the slice. In a customization step, the customer-designed function is merged with the pre-defined blocks and the metal layers (or late-metal components) are laid down, which couple the elements that make up the slice built in the wafer fab, and the customizable transistor array is configured and given its characteristic function. In other embodiments, early-metal steps may be part of the pre-fabricated slice to reduce the time and cost of the customization step, resulting in a platform which is more coupled and specific. It is understood that a prefabrication step and a customization step may be performed in different foundries. For example, a slice may be manufactured in one foundry. Later, in a customization step, the slice may be pulled from inventory and metalized, which gives the slice its final product characteristics in a different foundry.
A slice includes a number of IO, core macro, memory, and logic gate resources and may be used for a variety of applications. Each application may only use a subset of these resources. For example, a RapidSlice™ developed by LSI Logic Corp. may contain 600 IOs, 4M (1M=1 million) bits of memory, SERDES (Serializer/Deserializer) macros, and 5M logic gates. A particular graphics application (an instance of RapidChip™) using this slice may only require 500 of these 600 IOs, 4M bits of memory, no SERDES, and 4M logic gates, while a networking application using an identical slice may utilize all 600 IO circuits, less memory, all SERDES, and 2M gates. Unused IO resources need to be disabled since these can have implications on the interfaces to the customer's board, netlist, and testing environment.
One conventional approach to disable an unused IO circuit is to remove metal layers of the unused IO circuit. From a physical design perspective, metal interconnect may be removed from an unused IO device to effectively disable its operation for a given customer configurable application. From a logical perspective, this unused IO device is not included when the customer design netlist is created. However, this approach may have the following disadvantages. First, some IO devices, including those for mixed-signal circuits such as high speed SERDES interfaces, may exhibit high leakage currents if metallization is removed. This high leakage may unacceptable for any manufacturing test environment in addition to standard functional operation on the customer's system. Moreover, removing metal layers of an IO circuit assumes that all such layers are configurable for a given application (e.g., an instance of RapidChip™). In other words, all metal layers from METAL1 and upwards through the IO circuit must be modified for a given instance of the platform. This constraint increases the total mask cost of the instance and increases its overall NRE (Non-Recurring Engineering) cost.
Another conventional approach to disable an unused IO circuit is to ground it, float it, or tie it to a power source as appropriate to disable its functionality at the customer's circuit board level. Under this approach, an unused IO circuit remains physically present in the specific customer configurable application (e.g., an instance of RapidChip™). The unused IO circuit is fully metalized and operational and is preserved in the customer's logical design netlist. At the customer's circuit board level, the unused IO device is grounded, floated, or tied to a power source as appropriate to disable its functionality. However, this approach may have the following disadvantages. First, the customer must be educated and instructed on how to tie-off each specific unused IO resource. The unused IO resource may be tied to ground or power, or floated. In addition, tying unused IOs to power or ground forces the customer to give special circuit board design considerations to these IO resources, even though they are not being used. This introduces time, complexity, and cost to the circuit board design. Moreover, these unused IOs are preserved in the Instance design netlist. As a result, the customer must be sufficiently aware of these unused IOs even though they are not being used. This may be confusing to the customer, introduce mistakes, and create complexities in the customer's netlist generation process. Further, since the unused IO circuit is deemed functional, the unused IO circuit must be tested as part of the manufacturing test process. Consequently, test insertion logic and patterns must be created for the Instance of the platform. This introduces complexity in the design system, flow, and tools.
Thus, it would be desirable to provide a method and apparatus for disabling unused IO resources in a platform-based integrated circuit to address the foregoing-described problems.